High speed charge-coupled sampler and rate reduction circuit

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

357 24, 377 61, H03K 1704, H03K 1756, G11C 2702

Patent

active

050158767

ABSTRACT:
A high speed charge-coupled sampler and rate reduction circuit is disclosed. The present invention allows measurement of high frequency input signals while reducing actual data rates for a series of accurately interleaved sampler data streams. The charge-coupled sampler includes a source means for providing a steady supply of charge and a sampling gate means adjacent to the source means for dividing the charge stream into discrete charge packets separated uniformly in time. An input gate means, adjacent to the sampling gate means, modulates the discrete charge packets, such that size of each charge packet is directly proportional to the instantaneous voltage applied to the input gate means. A plurality of sequential charge output means in turn surround and are adjacent to the input signal gate means. Each sequential charge output means comprises a transfer gate and a storage gate for transferring and storing the charge packet modulated by the input gate means. Once a charge packet is stored by storage gate, it is available for further processing as part of that particular data stream. By interleaving the data streams from all sequential charge output means, the original input signal may be reconstructed. The high speed charge-coupled sampler and rate reduction circuit disclosed and claimed in this patent application provides an advanced, highly accurate and compact instrument for high frequency data acquisition and processing.

REFERENCES:
patent: 4099197 (1978-07-01), Ibrahim et al.
patent: 4123733 (1978-10-01), Poirier
patent: 4210825 (1980-07-01), Crochiere et al.
patent: 4259598 (1981-03-01), Tiemann et al.

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