System bus arbitration, circuitry and methodology

Details System bus arbitration, circuitry and methodology System bus arbitration, circuitry and methodology

1978-06-30

1981-03-17

Thomas, James D.

Boots, shoes, and leggings

G06F 300

Patent

active

042570956

ABSTRACT:
Arbitration of a system bus shared by a plurality of digital processors, input and output devices and memories may be shared in an intelligent and efficient manner by using an arbitration method and an arbiter and bus controller circuit which allows a lower priority processor or user to access the system bus during those times in which a higher priority user of the system bus is not actively accessing the system bus. Thus, without altering the priority assignments among multiple users of a system bus, lower priority users requesting access may be allowed selective and limited access to the system bus during those times in which a higher priority user is in either an idle or halt state or is engaged in utilizing another bus, such as an input/output bus or resident bus.

REFERENCES:
patent: 3825902 (1974-07-01), Brown et al.
patent: 3983540 (1976-09-01), Keller et al.
patent: 3995258 (1976-11-01), Barlow
patent: 4040028 (1977-08-01), Pauker et al.
patent: 4148011 (1979-04-01), McLagan et al.
patent: 4181974 (1980-01-01), Lemay et al.

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