Method of stabilizing holdover of a PLL circuit

Details Method of stabilizing holdover of a PLL circuit Method of stabilizing holdover of a PLL circuit

1999-04-22

2000-11-07

Mis, David

Oscillators

Automatic frequency stabilization using a phase or frequency...

Particular error voltage control

331 25, 327156, H03L 708, H03L 7093

Patent

active

061442615

ABSTRACT:
PLL (Phase Locked Loop) circuits have difficulty achieving both short pull-in time and stable hold-over time simultaneously. The PLL circuit of the present invention includes a first integrator and a second integrator. To reduce a pull-in time, feedback loop including the first integrator is provided with a sufficiently great loop gain. For stable holdover, a feedback loop including the second integrator is provided with a loop gain small enough to obviate the influence of the momentary variation of an input signal frequency.

REFERENCES:
patent: 5754607 (1998-05-01), Powell et al.

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