Error data correcting system

Excavating

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371 38, G06D 1110

Patent

active

043205100

ABSTRACT:
An input data signal, in which n data words W.sub.1 to W.sub.n and two check words P and Q are treated as one data block, is processed by P and Q decoding circuits. The decoded data S.sub.1 and T.sup.i-(n+1) S.sub.2 from the decoding circuits are added to each other in an adder to generate S.sub.1 +T.sup.i(n+1) S.sub.2 which is in turn selected by a gate circuit in accordance with a selection signal. The selection signal is supplied from an M matrix generator (MG) embodied as a linear feedback shift register for H(x)=X.sup.m +X.sup.g +1. The initial value of the linear feedback shift register is set in accordance with the error word data derived from an error word control circuit and the order of the data to be decoded. The decoded data sequentially selected from the gate circuit are added by an adder to be the data W.sub.je to be decoded, while at the same time those are added to the S.sub.1 by an adder to be the data W.sub.ie to be decoded. The data W.sub.je and W.sub.ie is added to the corresponding data words W.sub.i and W.sub.j of the input data signal having passed through a one-block delay circuit by an adder, whereby the error data are corrected.

REFERENCES:
patent: 3629824 (1971-12-01), Bossen
patent: 3697948 (1972-10-01), Bossen
patent: 3766521 (1973-10-01), Carter et al.
patent: 3868632 (1975-02-01), Hong et al.
patent: 4160236 (1979-07-01), Oka et al.
patent: 4242752 (1980-12-01), Herkert

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