Address sequence mechanism for reordering data continuously over

Details Address sequence mechanism for reordering data continuously over Address sequence mechanism for reordering data continuously over

1979-10-26

1982-03-16

Springborn, Harvey E.

Boots, shoes, and leggings

G06F 932

Patent

active

043204660

ABSTRACT:
A signal processor has a single random access memory having a capacity equal to or greater than the total number of words in a processing interval. An address sequence mechanism is operatively connected to the memory for addressing the memory in a sequence for, after the first processing interval, reading out data for the first processing interval continuously in a preselected output order and overwriting data for the next processing interval continuously in a preselected input order in the locations of the data being read out. An address checker is connected to the address sequence mechanism for checking the addresses thereof for error and a controller is operatively connected to the address sequence mechanism, address checker, and memory for controlling their operation.

REFERENCES:
patent: 3372382 (1968-03-01), Newman
patent: 3629857 (1971-12-01), Faber
patent: 4087626 (1978-05-01), Brader
patent: 4095266 (1978-06-01), Carubia et al.

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