Fault-tolerant memory system with graceful degradation

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371 403, 371 404, G06F 1110

Patent

active

052788474

ABSTRACT:
A fault-tolerating memory system has a data memory with a large number (M+N) of data storage words each having a length greater than the length of user data to be stored in that word; the extra word length is used for at least an error-detecting-and-correcting (EDAC) code. The user data is stored in a smaller number (N) of the words, with the remaining number (M) of words being used to store a map of which portions, if any, of each word are not usable. The N words of user data storage can include S normal storage words and (N-S) spare words, each for use if one of the normal storage words has too many unusable portions. A portion of each word length can contain at least one spare word portion, to which a block of data can be moved if any bit of a like-sized portion of the normal storage word is unusable. The reliability of storage is greatly improved by extension of each word to add EDAC encoding and spare-bit portions, as well as by extension of depth to allow spare words to be present, along with high-reliability storage of word maps.

REFERENCES:
patent: 4939694 (1990-07-01), Eaton et al.
patent: 4970648 (1990-11-01), Capots
patent: 5127014 (1992-06-01), Raynham
patent: 5134616 (1992-07-01), Barth, Jr. et al.

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