Square root operation device

Details Square root operation device Square root operation device

1992-06-03

1994-01-11

Nguyen, Long T.

Boots, shoes, and leggings

364748, G06F 738

Patent

active

052787826

ABSTRACT:
By taking a high-order position in an operand which is normalized in a two bit unit by means of and output from a normalizing circuit as an address, an approximation of square root's reciprocal is indexed by means of a table information storing unit. By multiplying an output of a residue holding circuit which takes a 0th residue as a normalized operand by the approximation of square root's reciprocal by using a multiplying circuit, a partial square root value is found. The individual partial square root values each having a overlapped bit at each iteration are merged with one another by means of a digit aligning circuit and an adder. A residue for a next step in iterative computation is found by subtracting a product of a merged square root value and a partial square root value from a residue by means of an inverting circuit, a multiplicand generator, a (R+S.times.T) operation unit.

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P. Montuschi et al., "On The Efficient Implementation Of Higher Radix Square Root Algorithms", Dipartimento di Automatica e Informatica, pp. 154-161, IEEE Symposium on Computer Arithmetic, 1989.

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