Voltage compensating CMOS input buffer

Details Voltage compensating CMOS input buffer Voltage compensating CMOS input buffer

1992-04-07

1994-01-11

Wambach, Margaret B.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072968, 307270, 307451, 307542, H03B 104, H03K 301

Patent

active

052784606

ABSTRACT:
The CMOS voltage compensating input buffer circuit of the present invention provides a means to stabilize input level trip points and is comprised of a voltage compensating circuit having an input node and an output drive node coupled to an input buffer. The voltage compensating circuit receives its input from a voltage adjusting circuit that follows changes in V.sub.CC while its output drive node is coupled to the series connected CMOS input buffer circuit having an input node and an output node. The buffer's input node receives a signal that VIH/VIL trip points will determine if the output is to be a high or a low and the buffer's output node then couples the resultant level to an output buffer circuit comprised of a CMOS inverter which provides the final output drive. The present invention provides trip point levels corresponding to industry standard VIH/VIL levels to accurately determine the corresponding output with operating voltage supplies (regulated or unregulated) operating between 2 V to 7.5 V.

REFERENCES:
patent: 5164621 (1992-11-01), Miyamoto

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