Static semiconductor memory using thin film FET

Details Static semiconductor memory using thin film FET Static semiconductor memory using thin film FET

1991-11-14

1994-01-11

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 365154, 257369, 257903, H03K 3356

Patent

active

052784592

ABSTRACT:
According to this invention, there is provided a semiconductor static data memorizing apparatus including, a first power supply terminal, a second power supply terminal, a first TFT (thin film transistor), the first TFT having a first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a first data storage node for memorizing the second data, a second TFT, the TFT having the first conductivity type, one terminal connected to the first power supply terminal, and the other terminal connected to a second data storage node for memorizing the data, a third TFT, the third TFT having a second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the first data storage node, and a fourth TFT, the fourth TFT having the second conductivity type, one terminal connected to the second power supply terminal, and the other terminal connected to the second data storage node, wherein a gate of the first TFT is connected to the second memory node, and a gate of the second TFT is connected to the first data storage node, such that a flip-flip circuit is formed by the first power supply terminal, the second power supply terminal, the first TFT, the second TFT, the third TFT, and the fourth TFT, and further including data bit lines which are inverted with respect to each other, a first switching device for performing a switching operation between one of the bit lines and the first data storage node, a second switching device for performing a switching operation between the other of the data bit lines and the second data memory, and a word line device, connected to gates of the first and second switching devices, for controlling operations of the first and second switching devices.

REFERENCES:
patent: 4045686 (1977-08-01), Masuda
patent: 4130892 (1978-12-01), Gunckel et al.
patent: 4740714 (1988-04-01), Musaki et al.
patent: 4980732 (1990-12-01), Okazawa
patent: 5134581 (1992-07-01), Ishibashi et al.
patent: 5157474 (1992-10-01), Ochii

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