Rounding operation circuit

Details Rounding operation circuit Rounding operation circuit

1993-03-22

1994-05-31

Nguyen, Long T.

Boots, shoes, and leggings

G06F 738

Patent

active

053175301

ABSTRACT:
A rounding operation circuit for arithmetic logic unit of a signal processor provided for counting fractions over 1/2 as one and disregarding the rest for the positive and negative number, which comprises a decoder circuit having an (n+1)-long input to which a first input signal represented by two's complement and a second n-bit long input signal for specifying the rounded position of the first signal are entered, when the first input signal is positive, a signal in which the bit at the rounded position is "1" and the rest is "0" is emitted based on the second input signal and, when the first input signal is negative, a signal in which the bits less significant than the bit at the rounded position are all "1" and the rest is "0" is emitted; arithmetic logic unit for adding the output signal of this decoder circuit and the first input signal; and a rounding circuit for counting 1 and cutting away 0 positively and negatively symmetrically to any rounding position, to allow a fast and accurate rounding operation.

REFERENCES:
patent: 3891837 (1975-06-01), Sunstein
patent: 4589084 (1986-05-01), Fling et al.
patent: 5218563 (1993-06-01), Juri et al.
CCITT SGXV WP XV/1 Specialist Group on Coding for Visual Telephony, Doc. #584, (1988-11), pp. 120-128.
Reverse DCT Operation in Motion Picture Processing VISP-LSI, Mochizuki et al., 1990, Telecommunication Assoc., National Conference Proceedings (Not Translated The Institute of Electronics, Information & Communication Engineers, Mar. 18-21, 1990, Tokyo, CHUO Univ. (Kasuga Campus)).
Assembly Language Instructions of Texas Instrument Third-Generation TMS320 User's Guide, 1988, pp. 11-141.
DSP56000/DSP56001 Digital Signal Processor User's Manual, by Motorola, Rev. 2, 1986, pp. A-191-A-193.

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