Method for producing a read-only memory having a plurality of MI

Details Method for producing a read-only memory having a plurality of MI Method for producing a read-only memory having a plurality of MI

1992-05-21

1994-01-11

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 48, 437 49, H01L 2170, H01L 2700

Patent

active

052780899

ABSTRACT:
A read-only memory device includes a number of MIS transistors forming memory cells arranged in a matrix configuration to provide a NOR type memory device with high current driving capability for the memory cells. Bit lines and column lines are arrayed alternately in common in each cell column so as to be used in common by adjacent memory cells in the word line extending direction. The bit lines for reading out signals from the memory cells function as the sources or drains of the MIS transistors of the memory cells, whereas the column lines for supplying the constant voltage to the memory cells function as the drains or sources of the MIS transistors of the memory cells. For column selection, there is provided a first selection switch for selecting a group consisting of a plurality of bit lines and a plurality of column lines. A second selection switch and a third selection switch are provided for selecting the bit line and the column line of the group, respectively. The second and the third selection switches may be arranged with a layout allowance and, if these second and third selection switches are formed by MIS transistors similar to those of the memory cells, the direction in common with the memory cells may be the channel direction to contribute to improved circuit integration. The MIS transistor constituting the memory cell may be of such a construction in which the source and drain regions may be provided below the thick insulating film formed on the substrate surface, such as field oxide film.

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