Fishing – trapping – and vermin destroying
Patent
1992-10-16
1994-01-11
Kunemund, Robert
Fishing, trapping, and vermin destroying
437 33, 437230, 148DIG11, 257197, 257571, 257584, 257586, H01L 2970
Patent
active
052780830
ABSTRACT:
Generally, and in one form of the invention, a method is disclosed for contacting a feature on an integrated circuit comprising: depositing a removable planarizing material 14 around the feature 10 so that a portion of the feature 10 extends above the removable planarizing material 14; depositing a masking layer 18 above the removable planarizing material 14, the masking layer 18 covering all but an exposed region above the feature 10 and an area around the feature; depositing an interconnect contact material 20 on the exposed region; and removing the masking layer 18 and the removable planarizing material 14, leaving the interconnect contact material 20 deposited on the exposed region, whereby a reliable, low capacitance, electrical contact is made to a very small feature 10.
REFERENCES:
patent: 4954457 (1990-09-01), Jambotkar
patent: 5166083 (1992-11-01), Bayraktaroglu
patent: 5168071 (1992-12-01), Fullowan et al.
Umesh K. Mishra et al., "Self-Aligned AiInAs-GaInAs Heterojunction Bipolar Transistors and Circuits," IEEE Electron Device Letters, vol. 10, No. 10, Oct. 1989, pp. 467-469.
Hill Darrell G.
Liu William U.
Donaldson Richard L.
Horton Ken
Kesterson James C.
Kunemund Robert
Skrehot Michael K.
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