Static information storage and retrieval – Addressing – Sync/clocking
Patent
1997-08-22
1998-09-22
Mai, Son
Static information storage and retrieval
Addressing
Sync/clocking
36518905, G11C 700
Patent
active
058124918
ABSTRACT:
A mode register control circuit for a semiconductor device includes a first control unit for preventing the content of a mode register from being read, using an initializing signal for instructing latching circuits to be initialized, the initialization being done in a transient occurring after the semiconductor device is turned on; a second control unit for instructing the mode register to execute a mode register read command even if a mode register set command has not been executed, on the condition that an external command other than the mode register read command is detected when the semiconductor device is turned on; or a third control unit for instructing the mode register to execute the mode register read command on the condition that the mode register set command is executed after the semiconductor device is turned on.
REFERENCES:
patent: 5036495 (1991-07-01), Busch et al.
patent: 5448528 (1995-09-01), Nagi
patent: 5526320 (1996-06-01), Zagar
patent: 5532961 (1996-07-01), Mori
patent: 5566108 (1996-10-01), Kitamura
patent: 5598376 (1997-01-01), Merritt
patent: 5617362 (1997-04-01), Mori et al.
Kanda Tatsuya
Shinozaki Naoharu
Fujitsu Limited
Mai Son
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