Nonvolatile semiconductor memory device and a writing method the

Details Nonvolatile semiconductor memory device and a writing method the Nonvolatile semiconductor memory device and a writing method the

1988-02-16

1990-02-20

Popek, Joseph A.

Static information storage and retrieval

Floating gate

Particular biasing

365218, G11C 1140

Patent

active

049032364

ABSTRACT:
In an erase mode, a high DC voltage Vpp is applied to all of the word lines and zero volt is applied to all of the bit lines, whereby the contents of all of the memory transistors are simultaneously erased. In a write mode, which constitutes an essential feature of the present invention, zero volt is applied to a selected word line and the high DC voltage Vpp is applied to a selected bit line, with an intermediate voltage 1/2.Vpp being applied to the other word lines and bit lines. Thus, by electron tunneling, data is written in a memory transistor located at a point of intersection between the selected word line and the selected bit line.

REFERENCES:
patent: 4377857 (1983-03-01), Tickle
patent: 4727515 (1988-02-01), Hsu

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