Method of making hot electron programmable, tunnel electron eras

Details Method of making hot electron programmable, tunnel electron eras Method of making hot electron programmable, tunnel electron eras

1989-12-29

1991-04-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 49, 437 52, 437195, H01L 21265

Patent

active

050100289

ABSTRACT:
An electrically-erasable, electrically-programmable, read-only memory cell array is formed in pairs at a face of a semiconductor substrate (11). Each memory cell includes a source region (14a) and a shared drain region (16), with a corresponding channel region (18a) in between. A Fowler-Nordheim tunnel window subregion (15a) of the source region (14a) is located opposite the channel (18a). A floating gate conductor (FG) includes a channel section (32a) and a tunnel window section (34a). The floating gate conductor is formed in two stages, the first stage forming the channel section (32a) from a first-level polysilicon (PlA). This floating gate channel section (32a/PlA) is used as a self-alignment implant mask for the source (14a) and drain (16) regions, such that the channel junction edges are aligned with the corresponding edges of the channel section. A control gate conductor (CG) is disposed over the floating gate conductor (FG), insulated by an intervening interlevel dielectric (ILD). The memory cell is programmed by hot carrier injection from the channel (18a) to the floating-gate channel section (32a), and erased by Fowler-Nordheim tunneling from the floating-gate tunnel window section (34a) to the tunnel window subregion (15a).

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patent: 4808261 (1989-02-01), Ghidini et al.
patent: 4853895 (1989-08-01), Mitchell et al.
patent: 4859619 (1989-08-01), Wu et al.
patent: 4924437 (1990-05-01), Paterson et al.

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