Boots – shoes – and leggings
Patent
1987-02-27
1990-02-20
Zache, Raulfe B.
Boots, shoes, and leggings
3642555, 3642462, 3642581, 3642553, 3642463, 364259, G06F 1202, G06F 1206
Patent
active
049031970
ABSTRACT:
A memory bank selection arrangement has a memory which is made up of smaller memories each of which has a number of banks of memory. First bits of a memory address are used by an address controller for addressing a location in a selected bank of a first of the smaller memories. The address may be incremented by the controller before being used to address a second of the smaller memories, and a carry output is generated when the first bits are incremented and there is a carry from the highest order bit thereof. The memory address also includes second bits which are input to an adder which increments the number represented by the second bits responsive to the carry out from the controller to compensate for the incrementation of said first bits. The incremented or unincremented number output from the adder is used by a selector to select a bank of the smaller memories so that they can be addressed using the incremented or unincremented first bits.
REFERENCES:
patent: 3813652 (1974-05-01), Elmer
patent: 4484265 (1984-11-01), Czekalski
patent: 4587637 (1986-05-01), Ishizuka
patent: 4698749 (1987-10-01), Bhadriraju
Lemay Richard A.
Wallace David A.
Bull HN Information Systems Inc.
Chan Emily Y.
Clapp Gary D.
Grayson George
Solakian John S.
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