Patent
1996-12-16
1998-10-27
Beausoliel, Jr., Robert W.
39518306, 39518322, 39518314, 39518317, G06F 1125
Patent
active
058288244
ABSTRACT:
A method of testing an integrated circuit 104 which may have multiple modules 204a-d is provided. Target interface 200 provides an interface for connecting target system 104 to a test system which is an extension of IEEE 1149.1. Target system 104 may have multiple devices 202, each having multiple modules 204. Each device 202 has device interface 210 which connects to target interface 200. Decoder 1020 decodes certain signals from interface 200 to enable Extended Operating Modes which allow test codes to be easily directed to any one of modules 204a-d. Hardware and software debugging of system 104 is aided by interface 200 and production testing of system 104 is simplified.
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Beausoliel, Jr. Robert W.
Donaldson Richard L.
Elisca Pierre E.
Laws Gerald E.
Marshall, Jr. Robert D.
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