Three overlapped stages of radix-2 square root/division with spe

Details Three overlapped stages of radix-2 square root/division with spe Three overlapped stages of radix-2 square root/division with spe

1995-07-05

1997-12-09

Elmore, Reba I.

Boots, shoes, and leggings

G06F 752

Patent

active

056967128

ABSTRACT:
In hardware SRT division and square root mantissa units maximal quotient selection overlapping for three quotient digits per cycle are used. An effective radix-8 implementation cascades three partial remainder computation circuits and overlaps three quotient selection circuits. Two carry save adders speculatively compute the possible resulting partial remainders corresponding to each possible value, -1, 0 , and +1, of the quotient digit by adding the divisor, not adding anything, and adding the two's complement of the divisor, respectively, thus shortening the critical path of a single SRT iteration producing a single quotient digit. The propagation delays of two carry save adders which speculatively compute the possible resulting partial remainders are masked by a longer delay through quotient selection logic.

REFERENCES:
patent: 3591787 (1971-07-01), Freiman et al.
patent: 4724529 (1988-02-01), Irukulla et al.
patent: 5404324 (1995-04-01), Colon-Bonet
G.S. Taylor, "Radix 16 SRT dividers with overlapped quotient selection stages", Proc. Seventh IEEE Symp. Compt. Arithmetic, pp. 64-71, 1987.
M.D. Ercegovac and T. Lang, "Division and Square Root: Digital-recurrence Algorithms and Implementations", Kluwer Academic Publishers, 1994, Ch. 3.
M.D. Ercegovac, T. Lang, J.G. Nash, L.P. Chow, "An Area-Time Efficient Binary Divider", Proc. IEEE International Conference on Computer Design, pp. 645-648, 1987.

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