Totally self-aligned CMOS process

Details Totally self-aligned CMOS process Totally self-aligned CMOS process

1985-12-20

1987-10-20

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, H01L 21265

Patent

active

047014237

ABSTRACT:
A CMOS process incorporates self-aligned buried contacts, lightly doped source/drain structures, and sidewall oxide spacers. The process is tailored so that individual process steps and structural features serve several functions, thereby providing the desirable structural features and small geometry in conjunction with fast operational speeds, reduced Miller capacitance and short channel effects in a process of minimum complexity.

REFERENCES:
patent: 4084311 (1978-04-01), Yasuoka et al.
patent: 4198250 (1980-04-01), Jecmen
patent: 4330931 (1982-05-01), Liu
patent: 4345366 (1982-08-01), Brower
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4391650 (1983-07-01), Pfeifer et al.
patent: 4419810 (1983-12-01), Riseman
patent: 4422885 (1983-12-01), Brower et al.
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4480375 (1984-11-01), Cottrell et al.
patent: 4503601 (1985-03-01), Chiao
patent: 4530150 (1985-07-01), Shirato
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4584027 (1986-04-01), Metz, Jr. et al.
patent: 4590663 (1986-05-01), Haken
patent: 4648175 (1987-03-01), Metz et al.
Tsang et al., "Fabrication of High-Performance LDDFET's With Oxide Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, vol. ED-29, No. 4, Apr. 1982, pp. 590-596.
Ogura et al., "Design And Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field Effect Transistor", IEEE Transactions on Electron Devices, vol ED-27, No. 8, Aug. 1980, pp. 1359-1367.
Ogura and Rovedo, "Latch-Up Free, Double Gated, Enhancement-Type P-Channel Device for CMOS With Enhanced Transconductance," IBM Technical Disclosure Bulletin, vol. 27, No. 1B, Jun. 1984, pp. 722-727.
Muramoto et al., "A New Self-Aligning Contact Process for MOS LSI," IEDM Technical Digest, 1978, pp. 185-188.
Mikkelson et al., "An NMOS VLSI Process for Fabrication of a 32-Bit CPU Chip", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1981, pp. 542-547.

Affiliated with

Also associated with

Rating

Totally self-aligned CMOS process does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Totally self-aligned CMOS process, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Totally self-aligned CMOS process will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1612394