Shared line direct write nonvolatile memory cell array

Details Shared line direct write nonvolatile memory cell array Shared line direct write nonvolatile memory cell array

1986-09-22

1988-09-06

Hecker, Stuart N.

Static information storage and retrieval

Floating gate

Particular biasing

365182, 365189, 365 72, G11C 1140, G11C 1134, G11C 700

Patent

active

047697881

ABSTRACT:
A memory array comprised of floating gate, direct write nonvolatile memory cells having cell interiors which are interconnected by successive adjacent rows to share column lines between adjacent columns of cell and thereby reduce the column line pitch.

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patent: 4628487 (1986-12-01), Smayling
patent: 4683554 (1987-07-01), Lockwood et al.
patent: 4698900 (1987-10-01), Esguivd
Miyamoto et al., "An Experimental 5-V-Only 256-Kbit CMOS EEPROM with a High-Performance Single-Polysilicon Cell", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 852-859.

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