Microprocessor architecture with a switch network for data trans

Details Microprocessor architecture with a switch network for data trans Microprocessor architecture with a switch network for data trans

1995-06-07

1997-02-18

Bowler, Alyssa H.

Boots, shoes, and leggings

39520005, 395481, 395800, 395856, 395878, 395860, 36423223, 3642328, 3642419, 364DIG1, G06F 1300

Patent

active

056048653

ABSTRACT:
A computer system comprising a microprocessor architecture capable of supporting multiple processors. Data transfers between data and instruction caches, I/O devices, and a memory are handled using a switch network. Access to memory buses is controlled by arbitration circuits which utilize fixed and dynamic priority schemes. A test and set bypass circuit is provided for preventing a loss of memory bandwidth due to spin-locking. A row match comparison circuit is provided for reducing memory latency by giving an increased priority to successive requests for access to memory locations having the same row address. Dynamic switch/port arbitration is provided by changing device priority based on the intrinsic priority of the device, the number of times that a request has been serviced based on a row match, the number of times that a device has been denied service, and the number of times that a device has been serviced.

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