Excavating
Patent
1994-11-01
1997-02-18
Beausoliel, Jr., Robert W.
Excavating
371 251, 371 226, 324765, 3241581, G01R 3128
Patent
active
056047509
ABSTRACT:
A method for improving the setup time of an integrated circuit tester when a device under test is to be tested includes maintaining the voltage settings for supply voltage (Vdd), voltage input low level (VIL), voltage output low level (VOL), voltage input high level (VIH), and voltage output high level (VOH) in a DRAM memory in the tester. Consequently, the tester data base keeps the image of the last hardware setup, which was used to operate a test sequence on a device under test (DUT). To reduce the time for effecting an integrated circuit test on a new test, the software code for the new test compares the various voltage settings for the new test with the stored voltage settings for the last hardware setup. No hardware operating changes are made whenever the compared voltage settings agree; and only voltage settings which are incorrect are changed in the hardware in a sequential comparison of the various voltages. This software check and comparison takes place in micro-seconds or nanoseconds.
REFERENCES:
patent: 4348759 (1982-09-01), Schnurmann
patent: 4903267 (1990-02-01), Arai et al.
patent: 5146161 (1992-09-01), Kiser
patent: 5359237 (1994-10-01), Pye
patent: 5402079 (1995-03-01), Levy
Beausoliel, Jr. Robert W.
Iqbal Nadeem
Ptak LaValle D.
VLSI Technology Inc.
LandOfFree
Method for voltage setup of integrated circuit tester does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for voltage setup of integrated circuit tester, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for voltage setup of integrated circuit tester will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1607379