Virtual interface representation of hierarchical symbolic layout

Details Virtual interface representation of hierarchical symbolic layout Virtual interface representation of hierarchical symbolic layout

1994-08-15

1997-02-18

Teska, Kevin J.

Boots, shoes, and leggings

364488, G06F 1750

Patent

active

056046804

ABSTRACT:
A method and system provide for the symbolic design of a symbolic layout of an integrated circuit using only the topological features of the cells of the layout, absent geometrical information. Virtual leaf cells define circuit elements, and virtual hierarchical cells combine virtual leaf cells and other virtual hierarchical cells into hierarchical arrangements using interface graphs. Virtual interfaces describe the connectivity and orientation relations between virtual cells. The interfaces inherit the definitional requirements of interfaces at lower levels. The symbolic layout is produced from a hierarchy of virtual cells using hierarchical compaction and routing technology.

REFERENCES:
patent: 4815003 (1989-03-01), Putatunda et al.
patent: 5262959 (1993-11-01), Chkoreff
patent: 5481473 (1996-01-01), Kim et al.
Gohar et al., "A New Schematic-Driven Floorplanning Algorithm for Analog Cell Layout", IEEE ISCAS, May 1993, pp. 1770-1773.
Jabri, "Automatic Building of Graphs Rectangularly Dualisable for Use in IC Floorplanning," ISCAS '88, pp. 1683-1686.
The et al., "Area Optimization for Higher Order Hierarchical Floorplans", ICCD '91, pp. 520-523.
Bamji et al. "A Design By Example Regular Structure Generator", 1985 22nd Design Automation Conference, Paper 2.3, pp. 16-21.
Barker et al. "The Development of a Graphical Environment for the Computer Aided Design of Control Systems," IEE Conference Publication 285, Control '88 pp. 81-86.
Boyer "Symbolic Layout Compaction Review," 1988 25th ACM/IEEE Design Automation Conference, Paper 26.1, pp. 383-389.
Costa et al. "Symbolic Generation of Constrained Random Logic Cells," IEEE Transactions on Computer-Aided Design, vol. 10, No. 2, Feb. 1991, pp. 220-231.
Costa et al. "Automatic Generation of Symbolic Cells from a Net-list Description," 1989 Proceedings of VLSI and Computer Peripherals, pp. 35-39.
Dutt et al. "On Minimal Closure Constraint Generation for Symbolic Cell Assembly," 1991 28th ACM/IEEE Design Automation Conference, Paper41.5, pp. 736-739.
Eades et al. "How to Draw a Directed Graph," 1989 IEEE Workshop on Visual Languages, pp. 13-17.
Gedye et al. "Browsing the Chip Design Database," 1988 25th ACM/IEEE Design Automation Conference, Paper 20.3, pp. 269-274.
Hou et al. "DECOMPOSER: A Synthesizer for Systolic Systems," 1988 25th ACM/IEEE Design Automation Conference, Paper 40.5, pp. 650-653.
Hsiao et al. "An Edge-Oriented Compaction Scheme Based on Multiple Storage Quad Tree," ISCAS '88, pp. 2435-2438.
Lo et al. "An O(n 1.5 logn) 1-d Compaction Algorithm," 1990 ACM/IEEE 27th Design Automation Conference, pp. 382-386.
Marple "A Hierarchy Preserving Hierarchical Compactor," 1990 27th ACM/IEEE Design Automation Conference, Paper 22.2, pp. 375-381.
Reichelt et al. "An Improved Cell Model for Hierarchical Constraint-Graph Compaction," 1986 IEEE Int'l Conference on Computer-Aided Design, pp. 482-485.

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