Software configurable memory architecture for data processing sy

Details Software configurable memory architecture for data processing sy Software configurable memory architecture for data processing sy

1987-11-24

1990-08-28

Harkcom, Gary V.

Boots, shoes, and leggings

364900, 3649274, 364964, 3649664, 364957, 3649575, G06F 1562

Patent

active

049531018

ABSTRACT:
A graphics data processing system memory is allocatable by software between system memory and graphics framebuffer storage. The memory comprises two-port elements connected in parallel from the RAM port to a controller connected to a bus, and having serial output ports connected to output circuitry to map the storage to a display. Corresponding locations, relative to element origin, in all elements are addressed in parallel as an array. Three modes of memory transactions are all accomplished as array accesses. First, a processor reads/writes the system memory portion by a combination of parallel array access and transfers between controller and bus in successive bus cycles. Second, the controller executes atomic graphics operations on the framebuffer storage using successive array accesses; third, the processor can read/write a framebuffer pixel, by an array access of framebuffer storage with masking of unaddressed pixels. An interface arbitrates among requests for memory access.

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patent: 3328768 (1967-06-01), Andahl et al.
patent: 4150364 (1979-04-01), Baltzer
patent: 4432067 (1984-02-01), Niesen
patent: 4701864 (1987-10-01), Takashima et al.
patent: 4773044 (1988-09-01), Sfarti et al.
Fuchs and Poulton "A VLSI-Oriented Design for a Raster Graphics Engine." Lambda 2(3):20-28, 1981.

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