Method for manufacturing an integrated circuit arrangement

Details Method for manufacturing an integrated circuit arrangement Method for manufacturing an integrated circuit arrangement

1997-12-15

2000-05-02

Bowers, Charles

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

428698, 428699, 428702, 428296, 428427, 428436, 428437, H01L 2176

Patent

active

060572116

ABSTRACT:
In a method for manufacturing an integrated circuit arrangement, trenches that define active zones are formed in a substrate. A first insulating layer that fills the narrow trenches is conformally deposited and is structured with a mask and anisotropic etching such that spacers arise at sidewalls of the wide trenches and supporting locations arise in a region of the wide trenches. The surface of the active zones is uncovered by forming a second insulating layer with an essentially planar surface and by a planarizing layer erosion on the basis of chemical-mechanical polishing or conventional dry etching.

REFERENCES:
patent: 4404735 (1983-09-01), Sakurai
patent: 4532701 (1985-08-01), Kameyama et al.
patent: 4965226 (1990-10-01), Gootzen et al.
patent: 5175122 (1992-12-01), Wang
patent: 5488007 (1996-01-01), Kim et al.
patent: 5643836 (1997-07-01), Meister
Forming Wide Trench Dielectric Isolation by P.J. Tsang, IBM Technical Disclosure Bulletin, vol. 25, No. 11B, Apr. 1983.
Method for Planarizing Over Shallow Trenches Filled with Silicon Dioxide, IBM Technical Disclosure Bulletin, vol. 32, No. 9A, Feb. 1990.
A New Planarization Technique, Using a Combination of RIE and Chemical Mechanical Polish (CMP) by B. Davari et al., IBM Research, et al. IEEE 1989.
A Novel Global Planarization Technology Using Defocused Resist Patterning with Blanket Stripe Mask (DRESS), by Y. Matsubara et al. ULSI Device Development Laboratories, IEEE 1993.
Patent Abstracts of Japan-02143461-Jan. 6, 1990.
Patent Abstracts of Japan-01030243-Jan 2, 1989.

Affiliated with

Also associated with

Rating

Method for manufacturing an integrated circuit arrangement does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing an integrated circuit arrangement, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing an integrated circuit arrangement will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1593373