Logic integrated circuit for scan path system

Details Logic integrated circuit for scan path system Logic integrated circuit for scan path system

1987-12-22

1989-10-24

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular input circuit

377 47, 377 54, 377 75, 377 77, 371 25, 324 73R, G01R 3128, G11C 1900

Patent

active

048767042

ABSTRACT:
A logic integrated circuit of the scan path system comprises a combination circuit and a shift register associated to the combination circuit and including a plurality of cascaded flipflops. The shift register has a scan input, a clock input, a scan control input, and a scan output. A scan input terminal is connected to the scan input of the shift register, and a clock terminal is connected to the clock input of the shift register. A scan output terminal is connected to the scan output of the shift register. Further, there is provided a counter having an input connected to the clock terminal and an output connected to the scan control input of the shift register. This counter has a frequency division ratio equivalent to the stage number of the flipflops in the shift register, so that the shift register is switched between a shift register mode and a normal mode by the frequency division signal from the counter.

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Williams et al., "Design for Testability-A Survey", IEEE Transactions on Computers, vol. C.31, No. 1, Jan. 1982, pp. 2-15.

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