Method of making self-aligned gate MOS device having small chann

Details Method of making self-aligned gate MOS device having small chann Method of making self-aligned gate MOS device having small chann

1982-01-26

1983-09-06

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 29578, 148187, 357 91, H01L 21302, H01L 2126, H01L 2978

Patent

active

044027613

ABSTRACT:
A semiconductor structure wherein a masking layer is formed to cover a portion of a surface of a semiconductor. A first doped region is formed in a portion of the semiconductor exposed by the masking layer. A chemical etchant is brought into contact with the masking layer, reducing the area of the masking layer covering the semiconductor exposing a second, different portion of the semiconductor contiguous to the first exposed portion of the semicoductor. Particles capable of establishing a doped region in the semiconductor layer are introduced into the second, different exposed portion of the semiconductor to form a second doped region in the semiconductor contiguous to the first doped region, such chemically etched masking layer inhibiting such particles from becoming introduced into the portion of the semiconductor disposed beneath the chemically etched masking layer. With such methods a self-aligned gate region may be formed in a field effect device having small channel lengths.

REFERENCES:
patent: 4069067 (1978-01-01), Ichinohe
patent: 4209349 (1980-06-01), Ho et al.
patent: 4214359 (1980-07-01), Kahng
patent: 4258465 (1981-03-01), Yasui et al.
patent: 4282646 (1981-08-01), Fortino et al.
patent: 4305201 (1981-12-01), Tiefert
Bassous et al., IBM-TDB, Apr. 1980: 22(11), p. 5146.

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