Semiconductor device manufacture including trench formation

Details Semiconductor device manufacture including trench formation Semiconductor device manufacture including trench formation

1989-05-05

1990-08-28

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437240, 437982, H01L 2176

Patent

active

049525247

ABSTRACT:
A trench which provides electrical isolation between transistors on an integrated circuit substrate is described. The trench is lined with a diffusion barrier, typically a thermal oxide followed by a thermal stress relief layer, typically formed from TEOS. Then a filler material, typically BPTEOS, is deposited to fill the trench and cover the upper surface of the wafer. The filler material is heated to make it flow. Next the outer surface of the flowed filler material is next subjected to an etch-back which makes the top surface of the filled trench protrude slightly above the upper surface of the substrate. The resulting trench contains the diffusion barrier layer, the thermal stress relief layer, and the filler material. The filler material and the thermal stress relief layer will soften during subsequent heat treatments of the wafer, thus relieving thermal stresses, and preventing the occurrence of defects and dislocations within the wafer.

REFERENCES:
patent: 4506435 (1985-03-01), Pliskin et al.
patent: 4543706 (1985-10-01), Bencuya et al.
patent: 4571819 (1986-02-01), Rogers et al.

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