Sequential data block address processing circuits

Details Sequential data block address processing circuits Sequential data block address processing circuits

1981-01-21

1984-12-04

Chin, Tommy P.

Facsimile and static presentation processing

Facsimile

Specific signal processing circuitry

358339, 360 362, 371 37, H04N 593

Patent

active

044867808

ABSTRACT:
A sequential data block address processing circuit for deriving address signals in dependence on incoming data which comprises sequential blocks of data each including an address signal representing a number, the numbers changing cyclically from block to block, for example where the incoming data is derived from a video tape recorder and represents video information comprising sequential blocks of data each representing a horizontal line scan of video information and each including a line address signal, the circuit comprising an address counter to generate output address signals corresponding to the incoming address signals and likewise changing cyclically from block to block under control of a signal derived from an oscillator and supplied by way of a counter operating as a frequency divider, and an arrangement formed by three latch circuits, an add and delay device, a line address comparator, and a counter for synchronizing the output address signals relative to the incoming address signals only when a predetermined plurality of the incoming address signals have been correctly received.

REFERENCES:
patent: 4180070 (1979-04-01), Taylor
patent: 4215368 (1980-07-01), Flory
patent: 4282550 (1981-08-01), Coviello
patent: 4302776 (1981-11-01), Taylor

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