Semiconductor device with delta-doped layer in channel region

Details Semiconductor device with delta-doped layer in channel region Semiconductor device with delta-doped layer in channel region

1993-02-11

1996-01-30

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Heterojunction device

Field effect transistor

257 24, 257 27, 257192, H01L 2712, H01L 29267, H01L 2980

Patent

active

054882370

ABSTRACT:
A high speed transistor featured by a wide operation range and a high gain has a channel layer of a three-layer structure wherein undoped GaInAs layers are arranged above and beneath a GaAs layer. The GaAs layer includes at least one n-type delta doped layer. A cap layer, which is an undoped GaAs layer, and a buffer layer are formed above and beneath the channel layer on the substrate. A gate electrode and a source region, a drain region, a source electrode and a drain electrode which are self-aligned with respect to the gate electrode, also are formed.

REFERENCES:
patent: 4833508 (1989-05-01), Ishikawa et al.
patent: 4862228 (1989-08-01), Ralph
patent: 5023674 (1991-06-01), Hikosaka et al.
Schubert et al., "Selectively S-Doped Al Ca As/ As Ga.sub.2 Heterostructures with high 2 Deg>, 1.5.times.10.sup.12 cm.sup.-2 For Field Effect Transistors," App. Phys. Lett., vol. 51, No. 15, 12 Oct. 1987, pp. 1170-1172.

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