Method for the manufacture of a MESFET comprising self aligned g

Details Method for the manufacture of a MESFET comprising self aligned g Method for the manufacture of a MESFET comprising self aligned g

1988-09-22

1989-12-26

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 44, 437 45, 437176, 437175, 437203, 437238, 437912, 148DIG139, 148DIG140, 148DIG168, 357 22, H01L 21316, H01L 21283

Patent

active

048898279

ABSTRACT:
A method for the manufacture of a MESFET comprising a gate that is self-aligned both with respect to the source and drain regions as well as with respect to the appertaining metallizations, whereby a first metal layer (21), a first dielectric layer (31), and a first lacquer mask layer are applied following doping of the carrier substrate. A trench producing an outer recess in the doping layer (11) is formed by anisotropic etching. A second dielectric layer is isotropically deposited and is anisotropically re-etched except for spacers (51/52) whereby an inner recess (double recess) is produced in the doping layer and, finally, the gate metal (22) is applied.

REFERENCES:
patent: 4472872 (1984-09-01), Toyoda et al.
patent: 4551905 (1985-11-01), Chao et al.
patent: 4616400 (1986-10-01), Macksey et al.
patent: 4774206 (1988-09-01), Willer
IBM Technical Disclosure Bulletin, "Self-Aligned Recessed Gate MESFET", vol. 28, No. 3, Aug. 1985, pp. 916-917.
C. E. Weitzel et al., "A Review of GaAs MESFET Gate Electrode Fabrication Technologies", Journal of the Electrochemical Society, Oct. 1986, pp. 409C-416C.
Yokoyama et al., "A Self-Aligned Source-Drain Planar Device for Ultra-High Speed GaAs MESFET VLSIs", IEEE International Solid State Circuits Conference, 1981, pp. 218-219.

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