Memory testing device

Details Memory testing device Memory testing device

1988-12-30

1990-09-18

Smith, Jerry

Excavating

371 251, 371 27, G06F 1100

Patent

active

049583468

ABSTRACT:
A device for testing a memory into which data can be written in a flash mode, includes a buffer memory which has a storage capacity equal to that of the memory under test, and a pattern generator for generating an address and data for input into the buffer memory. A data register stores the same data as that which is written into the memory under test during its flash write. A multiplexer selects either one of the data stored in the data register and the data from the pattern generator, and provides the selected data to the buffer memory. A logical comparator receives, as an expected value, data read out of the buffer memory and makes a logical comparison between it and data read out of the memory under test.

REFERENCES:
patent: 4369511 (1983-01-01), Kimura
patent: 4370746 (1983-01-01), Jones
patent: 4389677 (1983-06-01), Rushby
patent: 4775857 (1988-10-01), Staggs
patent: 4788684 (1988-11-01), Kawaguchi
patent: 4807229 (1989-02-01), Tada
patent: 4835774 (1989-05-01), Ooshima

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