Patent
1989-06-12
1990-09-18
Hille, Rolf
357 43, 357 51, H01L 2904, H01L 2702
Patent
active
049582135
ABSTRACT:
A process for fabricating an integrated circuit with both bipolar and CMOS transistors is disclosed. Buried n-type and p-type layers are diffused into a substrate, and a substantially intrinsic epitaxial layer is formed above the buried layers. N-wells and p-wells are formed into the epitaxial layer self-aligned relative to one another, over their respective buried layers. The intrinsic epitaxial layer allows the formation of the p-well, into which n-channel MOS transistors are eventually formed, with minimal mobility degradation due to counterdoping. Isolation oxide regions are formed at the boundaries of the wells, for isolation of the wells relative to one another. Trench isolation may alternatively be used, such trenches including polysilicon plugs which are recessed into the trench, and filled with an oxide layer to allow the placement of contacts over the trench with minimal overetch-induced or stress-induced leakage.
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Eklund Robert H.
Havemann Robert H.
Comfort James T.
Fahmy Wael
Hille Rolf
Sharp Melvin
Stoltz Richard A.
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