Data processor having a cache memory capable of being used as a

Details Data processor having a cache memory capable of being used as a Data processor having a cache memory capable of being used as a

1993-04-05

1995-04-25

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 3642434, 36424341, 364245, G06F 1208

Patent

active

054106699

ABSTRACT:
A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage of actual data, in the SRAM mode, or for storage of a set of tag entries in the cache mode. A module configuration register (40) specifies the mode of each set/bank. A set of base address registers (41-44) define the upper bits of a base address of SRAM banks. In SRAM mode, comparison logic (66) compares a tag field of the requested address (50) to the base address to determine an access hit. The least significant bit of the address, tag field is used to select either the tag store array (58) or the line array (60) for the requested address data read or write.

REFERENCES:
patent: 5067078 (1991-11-01), Talgam et al.
Lai, Konrad et al, "Revisit the case for direct-mapped caches: A case for two-way set associative level-two caches", 19th International Symposium on Computer Architecture, May 1992.

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