Semiconductor device having a plurality of CMOS I/O cells locate

Details Semiconductor device having a plurality of CMOS I/O cells locate Semiconductor device having a plurality of CMOS I/O cells locate

1983-01-05

1986-05-27

Edlow, Martin H.

357 41, 357 68, H01L 2702, H01L 2348

Patent

active

045918945

ABSTRACT:
A semiconductor device comprises a gate array portion formed in the central portion of a chip, and a number of CMOS input/output cells arranged at the peripheral portion of the chip. Each input/output cell consists of a bonding pad, a p-channel MOS region and an n-channel MOS region, and extends inward from the side of the chip in a direction perpendicular to the side of the chip.

REFERENCES:
patent: 4443811 (1984-04-01), Tubbs et al.
CMOS Design Manual (Interdesign) 1978, Chap. 5, Sec. 3, 2, The Buffer Cell, pp. 5-7.

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