Low di/dt output buffer with improved speed

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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307443, 3072966, 323312, 323314, 323315, H03K 494, H03K 1716

Patent

active

049580868

ABSTRACT:
An output buffer in an integrated circuit comprising voltage regulator, a predriver, and an output stage. The integrated circuit comprises a chip and a package and interconnections therebetween. The voltage regulator is coupled to a first power supply voltage terminal and a second power supply voltage terminal, and provides a regulated voltage signal characterized as having a constant voltage substantially independent of fluctuations in voltage between the first power supply voltage terminal and the second power supply voltage terminal. The predriver receives the regulated voltage signal and a data input signal and provides a regulated predriven signal in response to the data signal. The output stage receives the regulated predriven signal and provides an output signal in response thereto. The output signal is driven onto a bonding pad of the device to provide an interconnection point between the chip and the package.

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"A 21-ns 32K.times.8 CMOS Static Ram with a Selectively Pumped p-Well Array" by Karl Wang et al., IEEE Journal of Solid State Circuits, vol. SC-22, No. 5, Oct. 1987.

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