Memory system and method for selective multi-level caching using

Details Memory system and method for selective multi-level caching using Memory system and method for selective multi-level caching using

1996-03-05

1997-11-18

Gossage, Glenn

395466, 395403, G06F 1208, G06F 1300

Patent

active

056896794

ABSTRACT:
A selective multilevel caching method and system including a main memory and a plurality of cache memories are disclosed. The main memory and cache memories are arranged in a multilevel hierarchy: the main memory is at the lowest hierarchical level; the cache memory that is coupled directly to the central processing unit (CPU) is at the highest hierarchical level; and the remaining cache memories are coupled in the hierarchy at intermediate hierarchical levels therebetween. Each hierarchical level contains cache logic as well as a cache memory. Each cache logic responds to a cache level code that is associated with an address specified in each CPU read or write data request. The cache level code specifies the highest hierarchical level at which data associated with the data request may be written. Each cache logic uses the cache level code to determine if data will be written to the cache memory at the same hierarchical level as that cache logic. Each CPU write request further includes a cache control code. The cache control code indicates whether each cache level is designated as a write-allocate cache level. Each cache logic responds also to the cache control code to further determine if data will be written to the cache memory at the same hierarchical level as that cache logic.

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