Method and apparatus for generating test sequence

Details Method and apparatus for generating test sequence Method and apparatus for generating test sequence

1993-03-26

1995-04-25

Voeltz, Emanuel T.

Excavating

371221, 371 23, G06F 1100

Patent

active

054105528

ABSTRACT:
Disclosed is a method and apparatus for generating a test sequence to test a fault in a digital circuit. According to this method and apparatus, when a fault propagation process for a fault, for which a test sequence is generated is not successful, at least a segment of a path to propagate the effects of the fault is memorized as illegal information., And the fault propagation process is restarted for the same fault without selecting the illegal information. Hence, the chance of a successful fault propagation process is increased, which leads to the improvement of the fault coverage. In addition, according to the apparatus and method, it is detected whether a state transition goes into a loop (i.e., two identical states exist) in the state initialization process and then the process is restarted by defining the state caused the loop as an illegal state. Hence, the chance of a successful state initialization process is increased, which leads to the improvement of the fault coverage.

REFERENCES:
patent: 4204633 (1980-05-01), Goel
patent: 4696006 (1987-09-01), Kawai
patent: 4937826 (1990-06-01), Gheewala et al.
patent: 4996689 (1991-02-01), Samad
Fault Tolerant Computing: Theory and Techniques, vol. I, Chapterl, 1.4.2, issued by Prentice-Hall, Englewood Cliff, N.J., 1986.
Hitec: A Test Generation Package for Sequential Circuits, by T. Niermann et al., as a refernece of European Design Automation Conference in 1991.

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