1995-02-06
1997-11-18
Eng, David Y.
395563, G06F 900, G06F 1300
Patent
active
056896530
ABSTRACT:
The op-code bandwidth limitation of computer systems is alleviated by providing one or more vector buffers. Data is transferred between memory and processor registers in a two part process using the vector buffers. In a first part, a vector request instruction initiates buffering of data by storing data in control registers identifying a set of data elements (a vector) in the memory. When the identifying information is loaded in the control registers, a vector prefetch controller transfers elements of the vector between the memory and a vector buffer. In a second part, vector element operation instructions transfer a next element of the vector between the vector buffer and a specified processor register for use in arithmetic or logic operations.
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Amerson Frederic C.
Brzezinski Dennis
Gupta Rajiv
Karp Alan H.
Worley, Jr. William S.
Eng David Y.
Hewlett--Packard Company
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