Self-aligned Bi-CMOS device having high operation speed and high

Details Self-aligned Bi-CMOS device having high operation speed and high Self-aligned Bi-CMOS device having high operation speed and high

1988-11-28

1990-09-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 56, 437 57, 148DIG9, 357 34, 357 42, 357 43, H01L 2100, H01L 2102, H01L 2122, H01L 2126

Patent

active

049578740

ABSTRACT:
A Bi-CMOS device comprises a first insulating layer formed on a principal surface of a semiconductor substrate to extend outwardly from an edge portion of a base region of a bipolar transistor and from an edge portion of each source/drain region of each MOS transistor. A first polycrystalline semiconductor layer is formed on and in contact with a surface area of the base region of the bipolar transistor and a surface area of each source/drain region of each MOS transistor so as to extend on the first insulating layer. A second insulating layer is formed to cover the first polycrystalline semiconductor layer, a base-emitter junction exposed at the principal surface of the substrate and a portion of each of the base region and the emitter region adjacent to the exposed base-emitter junction. The second insulating layer also covers an inside edge of each source/drain region of the MOS transistors, and portions of each source/drain region and a channel region adjacent to the inside edge. A second polycrystalline semiconductor layer is formed to cover a gate insulator of each MOS transistors and a portion of an emitter region of the bipolar transistor in contact with the emitter region, so as to extend on the second insulating layer.

REFERENCES:
patent: 4806499 (1989-02-01), Shiohara
patent: 4825275 (1989-04-01), Tomassetti
Kobayashi, Y., Biplar CMOS-Merged Technology for High-Speed 1-Mbit DRAM, IEEE Transact. on Elect. Devices, vol. 36, No. 4, Apr. 1989, pp. 706-711.
IBM Tech. Dis. Bull., Bipolar Device Incorporated into CMOS Technology; vol. 28, No. 9, Feb. 1986, pp. 3813-3815.
O, K., BiCMOS Process Utilizing Selective Epitoxy for Analog/Digital Applications, IEEE Trans. on Elect. Devices, vol. 36, No. 7, Jul. 1989, pp. 1362-1369.

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