Boots – shoes – and leggings
Patent
1995-11-28
1997-11-18
Trans, Vincent N.
Boots, shoes, and leggings
364489, 364488, G06F 1750
Patent
active
056894333
DESCRIPTION:
BRIEF SUMMARY
The present invention relates generally to computer aided design systems which facilitate the design of integrated circuits and particularly to computer aided design methods and systems for automatically compacting integrated circuit layouts so as to meet a different set of "design rules" than the design rules originally used for a specified circuit layout.
BACKGROUND OF THE INVENTION
Virtually all complex integrated circuits are designed with the use of computer aided design (CAD) tools. Some CAD tools, called simulators, help the circuit designer verify the operation of a proposed circuit. Another type of CAD tool, called a silicon compiler (also sometimes known as automatic layout or place and route systems), generates the semiconductor mask patterns from a detailed circuit specification. These semiconductor mask patterns for a particular circuit are commonly called the "circuit layout".
Circuit layouts have multiple overlapping mask layers for defining different mask levels (also called layout levels) of a semiconductor integrated circuit. For instance, some layers of the circuit layout will define the regions of the semiconductor substrate that are doped with N-type or P-type dopants, while other layers of the circuit layout will define regions in which materials are deposited on the top of the substrate, such as polysilicon and metal regions, while yet other layers will define apertures to be formed in various layers of material so as to form connections between layers of the semiconductor circuit.
Each layer of a circuit layout is defined as a set of polygons or cells. In some systems, the cells must be rectangles, but most circuit layout systems allow the use of trapezoids and/or polygons whose sides are all vertical, horizontal or at a 45-degree angle to such vertical and horizontal sides.
Typically, a circuit layout will be prepared for a particular set of design rules. For instance, one will often hear that a circuit was manufactured using "2 micron design rules" or "2 micro minimum critical dimensions". Such phrases mean that certain features of the circuit's layout have minimum widths of 2 microns. Later, a faster version of that same circuit may be manufactured using "1 micron design rules" or "1 micron minimum critical dimensions".
While a number of attempts have been made in the past to compress or compact circuit layouts using automated computer techniques, most such prior automatic circuit layout compression systems use graph theory or linear programming methods, and thus lose at least some of the useful information and optimizations in the original layout. In addition, many of the prior art techniques are unable to handle layouts that include polygons with sides at 45 degree angles, and most require so many computer operations as to be impractical commercially.
SUMMARY OF THE INVENTION
A computer-aided design system for compacting semiconductor circuit layouts to meet a specified set of design rules. The specified set of design rules may cause the circuit layout to be compressed or expanded, depending on differences between the design rules used for the original circuit layout and the design rules used during the compacting process.
The automated circuit layout compacting process begins by fracturing a specified circuit layout into a set of convex trapezoids and then storing the resulting trapezoids in a database, herein called the connectivity data structure, that denotes the boundaries of each trapezoidal cell, and the cell adjacent to each such boundary. Empty spaces between cells are also represented in the data structure.
For each cell boundary, the connectivity data structure stores data representing the beginning and end points of each boundary edge (line segment), as well as move data representing the distance by which each such edge has been moved. Neighboring cells on the same and related layers of the circuit layout share edges in the connectivity data structure, and edges share common points. As a result, when a point of a cell is moved, the shared point of each neighbo
REFERENCES:
patent: 5097422 (1992-03-01), Corbin, II et al.
patent: 5267177 (1993-11-01), Sato et al.
patent: 5281558 (1994-01-01), Bamji et al.
patent: 5309371 (1994-05-01), Shikata et al.
patent: 5315534 (1994-05-01), Schlachet
patent: 5416722 (1995-05-01), Edwards
Trans Vincent N.
VLSI Technology Inc.
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