Process for forming a semiconductor device having a capacitor

Details Process for forming a semiconductor device having a capacitor Process for forming a semiconductor device having a capacitor

Filed on

1992-10-13

Date issued

1995-04-25

Examiner

Chaudhuri, Olik

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437 60, 437919, H01L 2170, H01L 2700

Type

Patent

Status

active

Patent number

054098556

Description

ABSTRACT:
A method for making a semiconductor memory cell having a storage capacitor disposed between metallization layers. Field and active regions and transistor circuit elements are formed on a substrate, on which is formed an insulating layer. A bit line is formed through a contact formed in the insulating layer. Another insulating layer is formed and a contact is formed to a word line and transistor and a primary metallization layer is formed of a refractory metal or metal compound. An oxide and an insulating layer are formed, and a buried contact to a source/drain region of a memory access transistor is formed to have an oxide side wall, and the storage electrode, dielectric and plate electrode are formed thereon. A secondary metallization layer may also be formed.

REFERENCES:
patent: 5155057 (1992-10-01), Dennison et al.
patent: 5180683 (1993-01-01), Wakamiya et al.
Electrical Characterization of Textured Interpoly Capacitors for Advanced Stacked Drams by: Pierre C. Fazan and Akram Ditali; IEDM 1990, pp. 27.5.1-27.5.4.
Rugged Surface Poly-si Electrode and Low Temperature Deposited Si.sub.3 N.sub.4 for 64MBIT and Beyond STC Dram Cell by: M. Yoshimaru, J. Miyar N. Inoue, A. Sakamoto, S. You, H. Tamura and M. Ino; IEDM 1990, pp. 27.4.1-27.4.4.
A capacitor-Over-Bit-Line (COB) Cell with a Hemispherical-Grain Storage Node for 64 Mb DRAMS by: M. Sakao, N. Kasai, T. Ishijima, E. Ikawa, H. Watanabe, K. Terada and T. Kikkawa; IEDM 1990; pp. 27.3.1-27.3.4.

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