Fishing – trapping – and vermin destroying
Patent
1994-03-09
1995-04-25
Fourson, George
Fishing, trapping, and vermin destroying
437186, 437203, H01L 21265
Patent
active
054098505
ABSTRACT:
In a MOS type semiconductor device, a source region, a channel region and a drain region of a MOS type device are arranged on the same plane, while a gate electrode is also arranged on the same plane adjacent to the channel region. Another set of a source region, a channel region and a drain region may also be arranged on the same plane and the latter MOS device is arranged to the gate electrode. This type of device may be constructed as a CMOS type device.
In another type of semiconductor device, the above-mentioned type plane arrangement of the source, channel and drain regions are layered via an insulator layer, while a gate electrode is provided vertically so as to be adjacent to the two channel regions.
REFERENCES:
patent: 4768076 (1988-08-01), Aoki et al.
patent: 4980308 (1990-12-01), Hayashi et al.
patent: 5096845 (1992-03-01), Inoue
H. Hieda et al., "New Effects of Trench Isolated Transistor Using Side-Wall Gates", IEDM 87, pp. 736-739, 1987.
T. Tanaka et al., "Analysis of P.sup.+ Poly Si Double-Gate Thin-Film SOI Mosfets", IEDM91, pp. 683-686, 1991.
Fourson George
Mason David
Matsushita Electric - Industrial Co., Ltd.
LandOfFree
Method of manufacturing a high density semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a high density semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a high density semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1567256