Method for reducing the spacing between the horizontally adjacen

Details Method for reducing the spacing between the horizontally adjacen Method for reducing the spacing between the horizontally adjacen

1996-08-21

1997-11-18

Chaudhari, Chandra

Fishing, trapping, and vermin destroying

437 48, 437984, H01L 218247

Patent

active

056887051

ABSTRACT:
The spacing between the horizontally-adjacent floating gates of a "T-shaped" flash electrically programmable read-only-memory (EPROM) array is reduced beyond that which can be photolithographically obtained with a given process by covering the layer of polysilicon that forms the floating gates with two sacrificial layers, exposing strips of the polysilicon layer with a standard photolithographic process, forming spacers that protect a portion of the exposed polysilicon layer, and then etching the layer of polysilicon that remains exposed.

REFERENCES:
patent: 5023203 (1991-06-01), Choi
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5268320 (1993-12-01), Holler et al.
patent: 5290723 (1994-03-01), Tani et al.
patent: 5296410 (1994-03-01), Yang
patent: 5330938 (1994-07-01), Camerlenghi
patent: 5366913 (1994-11-01), Nakao

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