Silicon on insulator with active buried regions

Details Silicon on insulator with active buried regions Silicon on insulator with active buried regions

1993-10-18

1996-01-30

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 26, 437 63, 437 64, 437974, 148DIG12, 148DIG150, 156630, H01L 2176

Patent

active

054880122

ABSTRACT:
A method for forming patterned buried components, such as collectors, sources and drains, in silicon-on-insulator (SOI) devices. The method is carried out by epitaxially growing a suitable sequence of single or multiple etch stop layers ending with a thin silicon layer on a silicon substrate, masking the silicon such that the desired pattern is exposed, introducing dopant and activating in the thin silicon layer to form doped regions. Then, bonding the silicon layer to an insulator substrate, and removing the silicon substrate. The method additionally involves forming electrical contact regions in the thin silicon layer for the buried collectors.

REFERENCES:
patent: 3332137 (1967-07-01), Kenney
patent: 3506424 (1970-04-01), Pomerantz
patent: 3602981 (1971-09-01), Kooi
patent: 3944447 (1976-03-01), Magdo et al.
patent: 3959045 (1976-05-01), Antypas
patent: 4599792 (1986-07-01), Cade et al.
patent: 4601779 (1986-07-01), Abernathey et al.
patent: 4968628 (1990-11-01), Delgado et al.
patent: 5013681 (1991-05-01), Godbey et al.
patent: 5071792 (1991-12-01), Van Vonno et al.
patent: 5110748 (1992-05-01), Sarna
patent: 5234535 (1993-08-01), Beyer et al.
patent: 5244817 (1993-09-01), Hawkins et al.
R. A. Lemons et al. "Laser Crystallization On Si Films On Glass", Appl. Phys. Lett., vol. 40, pp. 469-471, 1982.
J. B. Laskey et al., "Silicon-on-Insulator (SOI) by Bonding and Etch-back", Dig. 1985 IEEE Int. Electron Devices Mtng., Dec. 1985, pp. 684-687.
L. J. Spangler et al., "A Technology for High-Performance Single-Crystal Silicon-on-Insulator Transistors", IEEE Elec. Device Lett., vol. EDL-8, No. 4, Apr. 1987, pp. 137-139.
T. W. Sigmon et al., "Nanosecond Thermal Processing for Ultra-High-Speed Device Technology", Mat. Res. Soc. Symp. Proc., vol. 158, 1990, pp. 241-253.
K. H. Weiner et al., "Low-Temperature Fabrication of p+-NDiodes with 300-521 Junction Depth," IEEE Electron Device Letters, vol. 13, No. 7, Jul. 1992, pp. 369-371.
Wolf, "Silicon Processing for the VLSI Era", vol. 2, Process Integration, Lattice press, 1990, pp. 75-76.

Affiliated with

Also associated with

Rating

Silicon on insulator with active buried regions does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Silicon on insulator with active buried regions, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Silicon on insulator with active buried regions will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-156494