Programmable circuits for test and operation of programmable gat

Details Programmable circuits for test and operation of programmable gat Programmable circuits for test and operation of programmable gat

1995-11-14

1997-07-22

Beausoliel, Jr., Robert W.

Excavating

371 222, 371 221, 371 225, G01R 3128

Patent

active

056510136

ABSTRACT:
A system for scan testing a programmable array of logic cells is provided. The storage circuits of the logic cells are converted into master/slave storage circuits and connected into a shift register for scan testing. The storage circuits require A, B and C clocks during operation. A programmable clock splitter is provided having a first configuration wherein user-supplied A, B and C clocks are provided directly to A, B and C clock inputs of the storage circuits. The programmable switch has a second configuration wherein the A clock is inactivated and the B and C clocks are derived from a single B or C clock signal source. A programmable switch is provided for programmably providing a clock from either the user-supplied A, B and C clock signal sources or an alternative clock signal source. The programmable clock splitter and switch include circuitry for deriving two clocks from alternate phases of a single input clock. Various configurations of the programmable clock splitter and switch are disclosed which provide differing levels of clock selectivity to the logic cells.

REFERENCES:
patent: 4063080 (1977-12-01), Eichelberger et al.
patent: 4140967 (1979-02-01), Balasubramanian et al.
patent: 4177452 (1979-12-01), Balasubramanian et al.
patent: 4225957 (1980-09-01), Doty, Jr. et al.
patent: 4404635 (1983-09-01), Flaker
patent: 4441075 (1984-04-01), McMahon
patent: 4476431 (1984-10-01), Blum
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4503386 (1985-03-01), DasGupta et al.
patent: 4504784 (1985-03-01), Goel et al.
patent: 4509008 (1985-04-01), DasGupta et al.
patent: 4553236 (1985-11-01), Zasio et al.
patent: 4635261 (1987-01-01), Anderson et al.
patent: 4684830 (1987-08-01), Tsui et al.
patent: 4749947 (1988-06-01), Gheewala
patent: 4761768 (1988-08-01), Turner et al.
patent: 4771285 (1988-09-01), Agrawal et al.
patent: 4780628 (1988-10-01), Illman
patent: 4780874 (1988-10-01), Lenoski et al.
patent: 4782283 (1988-11-01), Zasio
patent: 4855669 (1989-08-01), Mahoney
patent: 4857774 (1989-08-01), El-Ayat et al.
patent: 4893311 (1990-01-01), Hunter et al.
patent: 4980889 (1990-12-01), DeGuise et al.
patent: 5047710 (1991-09-01), Mahoney
patent: 5218245 (1993-06-01), Kohler et al.
patent: 5250852 (1993-10-01), Ovens et al.
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5285453 (1994-02-01), Gruodis
patent: 5291079 (1994-03-01), Goetting
patent: 5298805 (1994-03-01), Garverick et al.
patent: 5337255 (1994-08-01), Seidel et al.
patent: 5367551 (1994-11-01), Okumura et al.
patent: 5459735 (1995-10-01), Narimatsu
Wagner, P.T., "Interconnect Testing With Boundary Scan," Paper 2.2, 1987 International Test Conference, IEEE, pp. 52-57.

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