Memory subsystem wherein a single processor chip controls multip

Details Memory subsystem wherein a single processor chip controls multip Memory subsystem wherein a single processor chip controls multip

1996-11-25

1997-10-14

Harvey, Jack B.

395402, 395403, 395440, 395442, 395446, 39542105, G06F 930

Patent

active

056780206

ABSTRACT:
A memory subsystem and method for controlling an integrated circuit (IC) die with another IC die, and a computer system for use with the memory subsystem. The computer system uses a processor die to control the operation of a cache memory die. A dedicated interface is couple between the processor die and the auxiliary memory die to transfer information between the processor die and the auxiliary memory die. The processor die controls the auxiliary memory die using at least one micro-operation code transfer to the auxiliary memory die on a portion of the interface to specify at least one operation. The auxiliary memory die includes control logic that performs the operation and response to the micro-operation code. In this manner, the processor die controls the auxiliary memory die using the interface and the micro-operation code. The processor die and the cache memory die are contained in a single integrated circuit chip.

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Popescu, Val; Schultz, Merle; Spracklen, John; Gibson, Gary; Lightner, Bruce; Isaman, David, "The Metaflow Architecture", IEEE Micro, Jun. 1991, pp. Nos. 10-13 and 63-73.

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