Method of making double level polysilicon series transistor devi

Details Method of making double level polysilicon series transistor devi Method of making double level polysilicon series transistor devi

1982-01-26

1983-04-26

Ozaki, G.

Metal working

Method of mechanical manufacture

Assembling or joining

29591, 148187, H01L 2122

Patent

active

043808638

ABSTRACT:
A plurality of MOS transistors are formed as an integrated semiconductor device, adjacent transistors sharing a common source/drain region which is created by the edges of inverted regions beneath the gates of the transistors. These gates are first and second level polysilicon, with the second partly overlapping the first. On the opposite ends, the source and drain regions are formed by diffusion using the oxide under the first and second level poly as the diffusion mask.

REFERENCES:
patent: 4055444 (1977-10-01), Rao
patent: 4084108 (1978-04-01), Fujimoto
patent: 4099196 (1978-07-01), Simko
patent: 4213139 (1980-07-01), Rao
patent: 4240092 (1980-12-01), Kuo
patent: 4274012 (1981-06-01), Simko
patent: 4290077 (1981-09-01), Ronen
patent: 4319263 (1982-03-01), Rao

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