Method for manufacturing semiconductor device with multilayer wi

Details Method for manufacturing semiconductor device with multilayer wi Method for manufacturing semiconductor device with multilayer wi

1996-02-09

1997-07-22

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437225, 437231, H01L 2102

Patent

active

056503601

ABSTRACT:
The present invention provides a method for manufacturing a semiconductor device having a multilayer wiring structure, in which the step of forming an insulating film for covering a wiring layer is improved. In the method a wiring pattern is formed on an insulating film provided on a semiconductor substrate, SiH.sub.4 gas and H.sub.2 O.sub.2 are introduced into a reaction chamber in which the semiconductor substrate provided with the wiring pattern is placed, and are reacted with each other under a negative pressure of 665 Pa or less at a temperature falling within a range from -10.degree. C. to +10.degree. C., thereby forming a reflow SiO.sub.2 film of a reflow configuration on the wiring pattern such that it does not completely cover the wiring pattern, and a plasma CVD insulating film is continuously deposited on the reflow SiO.sub.2 film on the semiconductor substrate by plasma CVD under a negative pressure.

REFERENCES:
patent: 5192714 (1993-03-01), Suguro et al.
patent: 5382545 (1995-01-01), Hong
patent: 5444023 (1995-08-01), Homma
Dobson et al., "Advanced SiO.sub.2 Planarization Using Silane and H.sub.2 O.sub.2 ", Semiconductor International, pp. 85-88, 1994.
Matsuura et al., "Novel Self-planarizing CVD Oxide for Interlayer Dielectric Applications", IEEE, pp. 117-120, 1994.

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