Method of making an integrated circuit chip having an array of l

Details Method of making an integrated circuit chip having an array of l Method of making an integrated circuit chip having an array of l

1996-06-11

1997-07-22

Picardat, Kevin

Fishing, trapping, and vermin destroying

437 52, 437226, 149DIG29, H01L 2170

Patent

active

056503482

ABSTRACT:
A semiconductor device includes a configuration having an array of logic gates electrically connected with an array of input/output (I/O) circuit devices, and also electrically connecting with an array of connector pads by which electrical connection with the semiconductor device may be effected. The array of logic gates is linearly continuous and is unbounded along at least a first axis through to boundaries imposed an edge of the semiconductor wafer. The arrays of I/O circuit devices and connector pads are disposed adjacent, and in one embodiment parallel, to the array of logic gates. Integrated circuit structures including a customized number of individual logic gate elements may be easily provided by cutting a selected length from the strip-like portion of the array of logic gates. Requisite connector pad and I/O circuit features are provided by the adjacent arrays of I/O circuit devices and the adjacent array of connector pads.

REFERENCES:
patent: 4900283 (1990-02-01), Fukae
patent: 4997792 (1991-03-01), McClurg
patent: 5217916 (1993-06-01), Anderson et al.
patent: 5399505 (1995-03-01), Dasse et al.
patent: 5426060 (1995-06-01), Kawahara et al.

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